Digital transmission system with a double analog integrator Delta Sigma coder and a double digital integrator Delta Sigma decoder

ABSTRACT

Delta-Sigma noise-shaping coder with two analog integrators and Delta-Sigma decoder with two digital integrators. The coder comprises an operational amplifier with two analog integrators in its feedback loop and two cascaded flipflops both connected to the input of the operational amplifier through resistors having a predetermined ratio. The configuration of the integrators is particular and results of the identification of the z-transfer function of the coder to be designed with the p-transfer function of a known integrator (p, Laplace&#39;s variable). The decoder comprises a digital integrator-filter of order two and two cascaded flipflops both connected to the input of the filter through amplifiers having gains in a predetermined ratio.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally concerns PCM digital coding and decodingof speech signals and more particularly analog to digital error feedbackcoders which shape the spectral distribution of the quantizing error soas to reduce in-band noise.

More precisely, the invention concerns a digital transmission system,the transmit station of which includes a RC analog filter which limitsthe speech analog waveform to be transmitted to 4 kHz, a noise-shapingwaveform coder of order higher than one, which codes the limited analogspeech waveform into one-bit samples at an oversampling rate of 2.048MHz, a digital filter which brings the sampling rate from 2.048 MHz to 8kHz and the sample bit number from 1 to 12 and a compressor which bringsback the sample bit number from 12 to 8. The receive station includes anexpander which brings back the sample bit number from 8 to 12, a digitalfilter which oversamples the digital waveform from 8 kHz to 32 kHz, aDelta-Sigma digital decoder including a double integrator which convertsthe sampling rate from 32 kHz to 2.048 MHz and the sample bit numberfrom 12 to 1, and a RC analog low pass filter.

2. Description of the Prior Art

The use of Delta-Sigma coders in PCM A/D converters has been proposed inthe article "A single channel PCM coder" by J. D. Everard, IEEE, ICC1978, Toronto, June 1978. In this article, the writer proposes toconvert in the encode-direction the analog signal to digital form usinga modified Delta-Sigma modulator operating at 2.048 kMHz, thus producingcodewords with a single bit per sample magnitude. Conversion of thelinear PCM codewords to compressed PCM is accomplished using a furtherdigital transformation. In the decode-direction, the compressed PCMcodewords are processed through a compressed PCM to linear PCMconverter, then the linear PCM codewords are processed by a digitalDelta-Sigma modulator to produce a single bit per sample code at 2.048kMHz.

The sampling frequency of 2.048 kHz chosen by EVERARD does not allow tomeet in Delta-Sigma coders the signal to noise ratio specificationsrecommended by the Comite Consultatif Telegraphique et Telephonique forPCM transmission systems (see CCITT, orange book, Vol. III-2,recommendation G 711, 712).

It has been also observed (see "Improvements to the Delta-Sigmamodulators when used for PCM encoding" by J. D. EVERARD, ElectronicsLetters, July 22nd, 1976, Vo. 12, No. 15, pages 379-380) that thequantization noise distribution in Delta-Sigma modulators has anapproximately square low relationship with frequency up to half theDelta-Sigma modulator sample rate. The exact distribution is intimatelyrelated to the amplitude probability density function of the inputsignal in such a way that very low output signal levels result inincreased quantization noise within the signal band. This is undesirablefor a PCM encoder application since very large clock rates are requiredto maintain adequate performance. Therefore, it has been proposed toincrease the signal to noise ratio at low levels by injecting a jammingsignal at such a frequency that it is filtered by the digitalsubsampling filter. This process is not satisfactory since it increasesthe signal to noise ratio at low levels but deteriorates it at highlevels.

In brief, Delta-Sigma modulators used as A/D converters in PCM linkscannot meet the CCITT specifications if the sample rate is not higherthan 2.048 MHz and if the Delta-Sigma modulators are of the first order.

The object of the invention is to provide a Delta-Sigma coder of ordertwo which operates at substantially 2 MHz and meets the specificationsfor A/D converters in PCM links.

Another object of the invention is to provide a Delta-Sigma coder whichcomprises a single operational amplifier and a single adder means.

SUMMARY OF THE INVENTION

The invention concerns a Delta-Sigma noise-shaping coder with two analogentegrators and a Delta-Sigma decoder with two digital integrators. Thecoder comprises an operational amplifier with two analog integrators inits feedback loop and two cascaded flipflops both connected to the inputof the operational amplifier through resistors having a predeterminedratio. The configuration of the integrators is particular and results ofthe identification of the z-transfer function of the coder to bedesigned with the p-transfer function of a known integrator (p,Laplace's variable). The decoder comprises a digital intergrator filterof order two and two cascaded flipflops both connected to the input ofthe filter through amplifiers having gains in a predetermined ratio.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block-diagram of a noise-shaping coder as taught by StuartK. TEWKSBURY et al.;

FIGS. 2, 3 and 4 are prior art Delta-Sigma coders of the first andsecond orders;

FIG. 5 is a block-diagram of the noise-shaping coder with two analogintegrators according to the invention;

FIG. 6 is a curve showing the perturbation borne by a filteringfunction;

FIG. 7 shows the signal to noise ratio versus the signal amplitude forthe coder of the invention and for other coders of the prior art;

FIGS. 8 and 9 represent the decoder of the invention; and

FIG. 10 represents a PCM link embodying the coder of FIG. 5 and thedecoder of FIG. 8 together with subsampling and oversampling digitalfilters and compressor and expander of the number of bits defining thePCM codewords.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Noise-shaping coders are disclosed in the article of "Oversampled"linear Predictive and Noise-shaping Coders of Order N>1", by Stuart K.TEWKSBURY et Robert W. HALLOCK, IEEE Transactions on Circuits andSystems, Vol. Cas-25, No. 7, July 1978.

In FIG. 1 which is no other than FIG. 4 of the above article, B(z) is afeed-forward filter, C(z) a feedback filter and Q(z) is a quantifier.S(z), Y(z) and Q(z) are the z-transforms of the coder input samplesequence, the coder output sample sequence and the quantizing errorsequence. These quantities are related by

    Y(z)=[B(z) S(z)+Q(z)] /[1+B(z)C(z)]

The coder is a noise-shaping coder if

    Y(z)=S(z)+H.sub.NS (z)Q(z)                                 (1)

Equation (1) defines constraints on B(z) and C(z). The constraints are

    B(z)/[1+B(z)C(z)]=1                                        (2)

    H.sub.NS (z)=1/[1+B(z)C(z)]                                (2')

from which we obtain

    B(z)=1/[1-C(z)]                                            (3)

    H.sub.NS (z)=1-C(z)                                        (4)

The conventional Delta-Sigma coder of FIG. 2 is a noise-shaping coderwith an integrator of order one. In this case, we have

    B(z)=z.sup.-1 /(1-z.sup.-1)                                (5)

wherein B(z) is the z-transfer function of an integrator followed by ablocker of order zero. Further

    C(z)=1

Then

    Y(z)=z.sup.-1 S(z)+(1-z.sup.-1)Q(z)                        (6)

which, if we disregard z⁻¹ which is a mere delay, is of the form ofequation (2) which defines a noise-shaping coder.

Noise-shaping coders with integrator of order N=2 are represented inFIG. 3 which is no other than FIG.8of U.S. Pat. No. 4,107,669 issuedAug. 15, 1978 to Stuart Keene TEWKSBURY, modified in a manner well-knownto those skilled in the art and in FIG. 4 which is no other than theRitchce's form of noise-shaping coder represented on FIG. 13 in thearticle of TEWKSBURY previously cited. It is reminded that the gains ofthe amplifiers in FIG. 4 are equal to the coefficients of a power of abinome.

In the coders of FIGS. 3 and 4, there are at least two adders in thepath of the input signal between the input terminal and the quantifier.In the noise-shaping coder of the invention which comprises anintegrator of order two, there is only one adder and the integrator is aparticular integrator.

Before disclosing the coder of the invention in FIG. 5, we shall explainthe theoretical approach which was followed: As already said, thetransfer function B(z) of the feed-forward filter in a Delta-Sigma coderof order one comprises the z-transfer function of the integrator and thez-transfer function of the quantifier which is a blocker of order zero,a flipflop for example. This z-transfer function B(z) is given byequation (5).

Let us take for z-transfer function of the feed-forward filter of theDelta-Sigma coder of order two:

    B(z)=z.sup.-1 /(1-z.sup.-1).sup.2                          (7)

which is the simpler and the more feasible z-transfer function of ordertwo.

The noise shaping filter of order two has the z-transfer function

    H.sub.NS (z)=(1-z.sup.-1).sup.2                            (8)

(see article by TEWKSBURY, page 440, formule "4.1").

From formula (2)

    C(z)=(B(z)-1)/B(z)=(2-z.sup.-1)                            (9)

Therefore, with B(z) given by formula (7), C(z) given by formula (9) andH_(NS) (z) given by formula (8), the z-transfer function of the coder is

    Y(z)=z.sup.-1 S(z)+(1-z.sup.-1).sup.2 Q(z)                 (10)

which has the type of equation (1). It appears that the feedback filterC(z) must have a delay z⁻¹ which can be easily implemented by aflipflop.

The digital filter of order two having as its z-transfer functionequation (7) is implemented in the following manner. The z-transferfunction (7) is the z-transform of a function F(p) multiplied by thetransfer function of a blocker of order zero which is

    (1-e.sup.-pτ)/p

Therefore: ##EQU1## where p is the Laplace's variable F.

Whence ##EQU2##

The solution of the equation (11) is: ##EQU3##

The transfer function (12) can be implemented with a single operationalamplifier such as that represented in FIG. 5. The p-transfer function ofthe circuit in FIG. 5 is: ##EQU4## Equation (13) can be identified toequation (11) by taking:

    G=-16(R/R.sub.1)

    τ=1/f.sub.e =4i RC

The double integrator Delta-Sigma coder represented in FIG. 5 comprisesan operational amplifier 20 having in its feedback loop a doubleintegrator formed by two capacitors 21 and 22 in series and having acapacitance C and a resistor in parallel 23 having a resistance R. Theoutput of operational amplifier 20 is connected to two cascadedflipflops 24 and 25 whose outputs are connected to the input ofoperational amplifier 20 through resistors 26 and 27 having respectiveresistances R' and 2R'. The resistance value of resistor 27 is indeedtwice that of resistor 26 for allowing the two flipflops 24, 25 and thetwo resistors 26,27 to implement the feedback filter C(z):

    C(z)=2-z.sup.-1                                            (9)

The output terminal of the first flipflop 24 is Q and the outputterminal of the second flipflop 25 is Q for taking account of the signminus before z⁻¹ in formula (9).

Experiments made by the applicant have shown that, if the value ofresistor R' is chosen equal to the value R₁ of the input resistor 28,

    R'=R.sub.1

the voltage at the output of filter C(z) reach excessive values whichcan involve blocking. To avoid this drawback, instead of taking

    C(z)=2-z.sup.-1                                            (9)

one takes:

    C(z)=2(2-z.sup.-1)                                         (9')

Equation (10) then becomes: ##EQU5##

The modulus of the transfer function 1/T(z) ##EQU6##

This modulus is represented by a curve in FIG. 6. The transfer functiondoes not practically perturb the signal in the passband and does notpresent infinite peaks. Then it is convenient to take:

    R'=R.sub.1 /4

The performance of the coder of FIG. 5 is represented by curve 71 inFIG. 7. For comparison purpose, one has also represented the Delta-SigmaCoder of Everard without jamming signal (curve 72) and with jammingsignal (curve 73). For the three curves, the sample rate is equal to2.048 MHz.

It is to be noticed that, as already said, the coder of FIG. 5 onlycomprises a single operational amplifier and a single adder means.

The Delta-Sigma decoder of order two is represented in FIG. 8. In thisfigure, 80 designates a digital recursive filter of order two havingcoefficients respectively equal to 2 and -1. This digital filter has az-transfer function equal to

    1/(1-z.sup.-1).sup.2

which corresponds to a double integration. But while the integration inthe coder was an analog integration, it is, in the decoder, a digitalintegration.

The output of digital filter 80 is connected to two cascaded flipflops84 and 85 having respectively the same function as flipflops 24 and 25of the coder. These flipflops are connected to adding means 81 at thedecoder input through amplifiers 86 and 87, having respectively gains of2 and 4, and whose role is the same as resistors 26 and 27 of the coder.

In adding means 81, two binary numbers are added to the codewords whichhave different values according to whether the flipflops 84 and 85 arepassing or blocked. The states of flipflops 84 and 85 correspond to thesign bits of the reconstituted samples s_(n-1) * and s_(n) *.

The addition of these two numbers implements the feedback filter

    C(z)=2(2-z.sup.-1)=4-2z.sup.-1                             (9')

Let us assume that the codewords have the binary point just at the rightof their sign bit, i.e. are coded between -1 and +1 and therefore havingmoduli smaller than or equal to 1.

The following table gives in dependence on the sign bit y_(n-1) of thesample to be decoded and the binary value s_(n-1) * and s_(n) * of thereconstituted samples (or, which is the same thing, in dependence on thestates of the flipflops 84 and 85) the number to be added to thecodewords and the integral part (part at the left hand of the binarypoint) of the summation result b₁ b₂ b₃ b₄. The bits at the right handof the binary point remain unchanged since the numbers to be added areintegral numbers (2 or 6).

It can be checked in the table that ##EQU7##

The finite difference equation of the recursive filter of order two 80is:

    s.sub.n *=2 s.sub.n-1 *-s.sub.n-2 *+x.sub.n-1

x being the sample at the output of the adding means 81.

And, on the feedback path, we have:

    x.sub.n-1 =y.sub.n-1 -4(sign bit of s.sub.n-1 *)+2(sign bit of s.sub.n31 2 *)

FIG. 9 is a more detailed block diagram of the decoder of FIG. 8.

Register 811 receives y_(n-1), the sign bit of s_(n-1) * multiplied by 4and the sign bit of s_(n-2) * multiplied by 2 and gives x_(n-1).

Register 812 receives s_(n-1) * multiplied by 2 from adder 815.

Register 813 receives s_(n-2) * divided by 2 from register 812.

Adder 814 gives:

    x.sub.n-1 +2s.sub.n-1 *

And adder 815 gives:

    x.sub.n-1 +2s.sub.n-1 -s.sub.n-2 *

that is s_(n) * which, at the subsequent sampling period, is transferredinto register 812.

Referring now to FIG. 10, an analog to PCM coder unit and a PCM toanalog decoder unit for single channel according to the invention arerepresented.

The coder unit comprises an analog RC filter 1, a Delta-Sigma coder 2 oforder two including two analog integrators according to FIG. 5 andoperating at 2.048 MHz, a first subsampling digital filter 3 operatingat 16 kHz, a second subsampling digital filter 4 operating at 8 kHz anda 12 to 8 bit compressor 5.

The decoder unit comprises a 8 to 12 bit expander 6 operating at 8 kHz,an oversampling digital filter 7 operating at 32 kHz, a Delta-Sigmadecoder 8 of order two including two digital integrators according toFIG. 8 and operating at 2.048 MHz and an analog RC filter 9.

    __________________________________________________________________________            s.sub.n-1 *                                                                       s.sub.n *                                                                           s.sub.n-1 *                                                                       s.sub.n *                                                                           s.sub.n-1 *                                                                       s.sub.n *                                                                         s.sub.n-1 *                                                                       s.sub.n *                                     0   0     0   1     1   0   1   1                                     Sign of bit y.sub.n-1                                                                 add -2    add +6    add -6  add +2                                    __________________________________________________________________________    0       b.sub.1                                                                         b.sub.2                                                                         b.sub.3                                                                         b.sub.4                                                                           b.sub.1                                                                         b.sub.2                                                                         b.sub.3                                                                         b.sub.4                                                                           b.sub.1                                                                         b.sub.2                                                                         3 b.sub.4                                                                         b.sub.1                                                                         b.sub.2                                                                         b.sub.3                                                                         b.sub.4                                     =         =         =       =                                                 0 1 1 1 = 14                                                                            0 1 0 1   0 1 1 0 0 1 0 0                                   1       b.sub.1                                                                         b.sub.2                                                                         b.sub.3                                                                         b.sub.4                                                                           b.sub.1                                                                         b.sub.2                                                                         b.sub.3                                                                         b.sub.4                                                                           b.sub.1                                                                         b.sub.2                                                                         b.sub.3                                                                         b.sub.4                                                                         b.sub.1                                                                         b.sub.2                                                                         b.sub.3                                                                         b.sub.4                                     =         =         =       =                                                 1 0 1 1   1 0 0 1 = 9                                                                             1 0 1 0 1 0 0 0                                   __________________________________________________________________________     Example:                                                                      Let us add -2 to a codeword having a sign bit equal to 0 taking numbers o     4 bits. We substract 0 from the complement of 2 to 16. The result is 14 =     0111;                                                                         Let us add +6 to a codeword having a sign bit equal to 1. We substract 1      from the complement of 6 to 16. The result is 1001 = 9.                  

What we claim is:
 1. In an analog to PCM coding and a PCM to analogdecoding system, a Delta-Sigma noise-shaping codec operating at asampling rate of substantially 2 MHz, said codec comprising:aDelta-Sigma noise-shaping coder including a single operationalamplifier; an adding means receiving an analog signal and connected tosaid operational amplifier; two analog integrators in the feedback loopof said operational amplifier; a first and second cascaded flipflopsoperated at said sampling rate; a first resistor means connecting theoutput of said first flipflop to said adding means; a second resistormeans connecting the output of said second flipflop to said addingmeans; and output means connected to said second flipflop; and aDelta-Sigma decoder including two digital integrators; an adding meansreceiving a digital signal coded by said coder and connected to saiddigital integrators; a first and second cascaded flipflops operating atsaid sampling rate; a first amplifier means connecting the output ofsaid first flipflop to said adding means; a second amplifier meansconnecting the output of said second flipflop to said adding means; andoutput means connected to said second flipflop.
 2. Codec as set forth inclaim 1, wherein the two analog integrators in the feedback loop of theoperational amplifier comprises two serially connected capacitors and aresistor having an extremity connected to the common point of saidcapacitors and its other extremity grounded.
 3. Codec as set forth inclaim 1, wherein the two resistors means each comprise a resistor andthe resistance of one is double that of the other.
 4. Codec as set forthin claim 1, wherein the two resistor means each comprise a resistor, theoperational amplifier has an input serial resistor, and the resistor ofthe first resistor means is equal to said input serial resistor and theresistor of the second resistor means is equal to twice said inputserial resistor.
 5. Codec as set forth in claim 1, wherein theoperational amplifier has an input serial resistor, the two resistorsmeans each comprise a resistor and the resistor of the first resistormeans is equal to the fourth of said input serial resistor and theresistor of the second resistor means is equal to half said input serialresistor.
 6. Decoder as set forth in claim 1, wherein the firstamplifier means and the second amplifier means each comprise anamplifier and the gain of one is twice that of the other.